Esd protection device with reduced harmonic distortion

A semiconductor assembly, comprising:

• a circuit carrier comprising first and second planar die mounting pads;
• an overvoltage protection device mounted on the circuit carrier and comprising first and second semiconductor devices arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, the first and second semiconductor devices each being two terminal semiconductor devices with one way conduction characteristics,
• wherein a first conductive electrode of the overvoltage protection device is attached and electrically connected to the first planar die mounting pad,
• wherein a second conductive electrode of the overvoltage protection device is attached and electrically connected to the second planar die mounting pad,
• wherein a first transmission path exists between the second planar die mounting pad and the central node and a second transmission path exists between the second planar die mounting pad and the central node,
• wherein a self-capacitance of the conductive link contributes to a total capacitance of the second transmission path during operation of the overvoltage protection device,
• wherein the overvoltage protection device further comprises an additional capacitance in the first transmission path, and
• wherein the additional capacitance is greater than the self-capacitance of the conductive link.