Repairing lanes associated with memory devices
AssigneeMicron Technology, Inc.
InventorWoo Hyun PAIK
Life of this patent
Estimating the term…
Abstract
Implementations described herein relate to repairing lanes associated with memory devices. In some implementations, a memory device may detect, using a lane repair block, that a lane of the memory device is associated with a lane failure, wherein the lane repair block is employed prior to a first physical (PHY) latch that is between a through-silicon via (TSV) associated with the memory device and a data queue (DQ) pad associated with the memory device. The memory device may map, using the lane repair block, the lane associated with the lane failure to an alternate lane associated with one or more alternate blocks.
Claims25
A memory device, comprising:
- one or more components configured to:
- detect, using a lane repair block, that a lane of the memory device is associated with a lane failure, wherein the lane repair block is employed prior to a first physical (PHY) latch that is between a through-silicon via (TSV) associated with the memory device and a data queue (DQ) pad associated with the memory device;
- and
- map, using the lane repair block, the lane associated with the lane failure to an alternate lane associated with one or more alternate blocks.
A method, comprising:
- detecting, using a lane repair block associated with a memory device, that a lane of the memory device is associated with a lane failure, wherein the lane repair block is employed prior to a first physical (PHY) latch that is between a through-silicon via (TSV) associated with the memory device and a data queue (DQ) pad associated with the memory device;
- and
- mapping, using the lane repair block, the lane associated with the lane failure to an alternate lane associated with one or more alternate blocks.
An apparatus, comprising:
- means for detecting that a lane of a memory device is associated with a lane failure, wherein a lane repair block is employed prior to a first physical (PHY) latch that is between a through-silicon via (TSV) associated with the memory device and a data queue (DQ) pad associated with the memory device;
- and
- means for mapping the lane associated with the lane failure to an alternate lane associated with one or more alternate blocks.
Dependencies are inferred from the claim text.