Memory device

A memory device comprising:

• a memory circuit including a plurality of memory cell blocks each including a plurality of memory cells, and a plurality of sense amplifier circuits provided for the plurality of memory cell blocks, respectively;
• and
• a control circuit controlling the memory circuit,
• wherein
• each of the plurality of memory cells includes a variable resistance element and a switching element connected in series with the variable resistance element, and stores data corresponding to one of a low-resistance state and a high-resistance state of the variable resistance element,
• each of the plurality of sense amplifier circuits includes:
• a first circuit portion through which a first current flows, the first current depending on a first value obtained by a first read operation that reads target data stored in a selected memory cell of the plurality of memory cells;
• a second circuit portion through which a second current flows, the second current depending on a second value obtained by a second read operation that reads reference data written to the selected memory cell during a write operation performed after the first read operation;
• a third circuit portion connected in parallel to the second circuit portion, through which a third current flows when the second current flows through the second circuit portion;
• and
• an output portion which outputs a detection signal corresponding to the target data based on a relationship between a magnitude of the first current and a magnitude of a total current of the second current and the third current, and
• the control circuit includes an adjustment circuit which adjusts the third current flowing through the third circuit portion with respect to each of the plurality of sense amplifier circuits.