Reception apparatus, memory controller, and memory system

A memory controller which is connectable to a host and controls a semiconductor storage device, the memory controller comprising:

• a first sampler circuit configured to extract a first digital signal based on a first clock signal from a reception signal transmitted from the host;
• a second sampler circuit which uses the reception signal or a reference signal obtained by performing an adjustment on the reception signal and a second clock signal obtained by performing a phase adjustment on the first clock signal to extract a second digital signal based on the second clock signal from the reception signal or the reference signal;
• a conversion circuit which converts the second digital signal into a third digital signal synchronized with a phase of the first digital signal;
• a plurality of comparison circuits each of which is a circuit which shifts a bit sequence of the first digital signal by a predetermined number and counts a number of bit errors by comparing the bit sequence of the first digital signal shifted by the predetermined number with a bit sequence of the third digital signal and in which the predetermined number is set as a mutually different value;
• and
• a selection circuit which selects any one of the plurality of comparison circuits based on the plurality of numbers of bit errors respectively counted by the plurality of comparison circuits and detects the number of bit errors counted by the selected comparison circuit as an actual number of bit errors.

A memory system comprising:

• a semiconductor storage device;
• a memory controller which is connectable to a host and controls the semiconductor storage device;
• a first sampler circuit configured to extract a first digital signal based on a first clock signal from a reception signal transmitted from the host;
• a second sampler circuit which uses the reception signal or a reference signal obtained by performing an adjustment on the reception signal and a second clock signal obtained by performing a phase adjustment on the first clock signal to extract a second digital signal based on the second clock signal from the reception signal or the reference signal;
• a conversion circuit which converts the second digital signal into a third digital signal synchronized with a phase of the first digital signal;
• a plurality of comparison circuits each of which is a circuit which shifts a bit sequence of the first digital signal by a predetermined number and counts a number of bit errors by comparing the bit sequence of the first digital signal shifted by the predetermined number with a bit sequence of the third digital signal and in which the predetermined number is set as a mutually different value;
• and
• a selection circuit which selects any one of the plurality of comparison circuits based on the plurality of numbers of bit errors respectively counted by the plurality of comparison circuits and detects the number of bit errors counted by the selected comparison circuit as an actual number of bit errors.