Semiconductor apparatus, recording head, and writing method for memory circuit
AssigneeCanon Kabushiki Kaisha
InventorMASAO FURUKAWA
Life of this patent
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Abstract
Provided is a semiconductor apparatus that includes a memory circuit, the memory circuit including at least a first series-connected portion including a first antifuse element and a first fuse element connected in series, and a second series-connected portion including a second antifuse element and a second fuse element connected in series. The first series-connected portion and the second series-connected portion are connected in parallel. The first series-connected portion is connected in series to a first resistor element. The second series-connected portion is connected in series to a second resistor element.
Claims8
A semiconductor apparatus comprising a memory circuit, the memory circuit comprising at least:
- a first series-connected portion comprising a first antifuse element and a first fuse element connected in series;
- and
- a second series-connected portion comprising a second antifuse element and a second fuse element connected in series,
- wherein the first series-connected portion and the second series-connected portion are connected in parallel,
- wherein the first series-connected portion is connected in series to a first resistor element, and
- wherein the second series-connected portion is connected in series to a second resistor element.
A semiconductor apparatus comprising a memory circuit, the memory circuit comprising at least:
- a first series-connected portion comprising a first antifuse element and a first fuse element connected in series;
- and
- a second series-connected portion comprising a second antifuse element and a second fuse element connected in series,
- wherein the first series-connected portion and the second series-connected portion are connected in parallel, and
- wherein the semiconductor apparatus further comprises a counter circuit configured to count the number of times the memory circuit is rewritten.
A writing method for a memory circuit of a recording head, the memory circuit comprising at least a first series-connected portion including a first antifuse element and a first fuse element connected in series, and a second series-connected portion including a second antifuse element and a second fuse element connected in series, the writing method comprising:
- connecting the first series-connected portion and the second series-connected portion in parallel;
- connecting a first resistor element in series to the first series-connected portion;
- connecting a second resistor element in series to the second series-connected portion;
- writing to the first antifuse element during a first rewriting operation;
- and
- writing to the second antifuse element and disconnecting the first fuse element during a reuse of the recording head.
Dependencies are inferred from the claim text.