Semiconductor memory device

A semiconductor memory device comprising:

• a first source line extending in a first direction and a second direction intersecting the first direction;
• a local bit line extending in the second direction;
• a first bit line extending in the second direction and overlapping the local bit line when viewed from a third direction intersecting the first and second directions;
• a first-tier memory cell array including a plurality of first local strings arranged in the third direction, each of the plurality of first local strings including a first selection transistor, a plurality of first memory cells, and a second selection transistor arranged between the first source line and the local bit line and electrically connected in series;
• a second-tier memory cell array including a plurality of second local strings arranged in the third direction, each of the plurality of second local strings including a third selection transistor, a plurality of second memory cells, and a fourth selection transistor arranged between the local bit line and the first bit line and electrically connected in series;
• and
• a control circuit electrically connected to the first bit line and configured to control the first-tier memory cell array and the second-tier memory cell array.