Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including a plurality of word lines and a plurality of memory cells;
• a booster circuit configured to boost an input voltage to generate a first voltage and a second voltage higher than the first voltage;
• a first regulator configured to adjust one of the first voltage or the second voltage to output a third voltage;
• a second regulator configured to adjust one of the first voltage or the second voltage to output a fourth voltage;
• and
• a row decoder configured to apply a voltage to the plurality of word lines,
• wherein in a read operation of one of the memory cells connected to a selected word line among the plurality of word lines,
• the booster circuit is configured to switch a voltage to be generated from the first voltage to the second voltage in response to a non-select word line other than a word line adjacent to the selected word line among the plurality of word lines being boosted to the third voltage.