Efficient and high performance write architecture for high density resistive random access memory

A resistive random-access memory (ReRAM) device, comprising:

• a first array of bit cells, including bit cells arranged in a first number of rows and a second number of columns, the second number of columns being arranged in a first plurality of column groups, each column group of the first plurality of column groups including a third number of columns, wherein each bit cell has a control terminal and two current carrying terminals, each bit cell in a row has its control terminal coupled to a word line (WL) of the row, and each bit cell in a column has at least two current carrying terminals coupled, respectively, to a bit line (BL) and a source line (SL) of the column;
• global write drivers operable to drive signals to bit cells in respective columns in a selected column group of the first plurality of column groups;
• and
• a first plurality of local drive units corresponding, respectively, to the first plurality of column groups, a respective local drive unit of the plurality of local drive units including local multiplexing gates corresponding to respective columns in a respective column group, wherein each local multiplexing gate is coupled to the BL and SL of a respective column of the respective column group;
• wherein:
• the respective local multiplexing gate includes a first set of transistors, and the respective global write driver includes a second set of transistors corresponding, respectively, to the first set of transistors;
• a first transistor of the first set of transistors and a first corresponding transistor of the second set of transistors are serially connected between one of the SL and BL of the respective column and one of first and second supply voltage terminals of the ReRAM device;
• and
• a second transistor of the first set of transistors and a second corresponding transistor of the second set of transistors are serially connected between the other one of the SL and BL of the respective column and the other one of first and second supply voltage terminals.