Memory device including ternary memory cell

A memory device comprising:

• a memory cell array including at least two ternary memory cells each connected to a word line and a bit line pair including a bit line and an inverted bit line, the at least two ternary memory cells each storing first data having a ternary information system;
• bit line peripheral circuitry connected to each of the at least two ternary memory cells through the bit line pair, the bit line peripheral circuitry configured to read 1st′ data corresponding to a voltage value of the bit line pair corresponding to the first data stored in the memory cell array in a read mode and configured to write and store the first data corresponding to the 1st′ data corresponding to the voltage value of the bit line pair in the memory cell array in a write mode;
• and
• a code converter connected to the bit line peripheral circuitry, the code converter configured to receive the 1st′ data corresponding to the voltage value of the bit line pair from the bit line peripheral circuitry and convert the 1st′ data into second data having a binary information system in the read mode and configured to receive the second data, convert the second data into the 1st′ data corresponding to the voltage value of the bit line pair, and transmit the 1st′ data to the bit line peripheral circuitry in the write mode.