Multi-port static random access memory
AssigneeAvago Technologies International Sales Pte. Limited
InventorsEric William Eklund, Travis Hebig, Luke Robert Everson
Life of this patent
Estimating the term…
Abstract
An example memory circuit can include: a memory cell coupled to a first word line, a second word line, a first bit line, and a second bit line, the first word line selectively coupling the memory cell to the first bit line, the second word line selectively coupling the memory cell to the second bit line; a first sense amplifier coupled to the first bit line and a reference voltage, the first sense amplifier configured to compare voltage of the first bit line to the reference voltage; and a second sense amplifier coupled to the second bit line and the reference voltage, the second sense amplifier configured to compare voltage of the second bit line to the reference voltage.
Claims20
A memory circuit, comprising:
- a memory cell coupled to a first word line, a second word line, a first bit line, and a second bit line, the first word line selectively coupling the memory cell to the first bit line, the second word line selectively coupling the memory cell to the second bit line;
- a first sense amplifier coupled to the first bit line and a reference voltage, the first sense amplifier configured to compare voltage of the first bit line to the reference voltage;
- and
- a second sense amplifier coupled to the second bit line and the reference voltage, the second sense amplifier configured to compare voltage of the second bit line to the reference voltage.
A memory circuit, comprising:
- an array of memory cells;
- and
- a controller coupled to the array of memory cells;
- the array of memory cells including:
- a memory cell coupled to a first word line, a second word line, a first bit line, and a second bit line, the first word line selectively coupling the memory cell to the first bit line, the second word line selectively coupling the memory cell to the second bit line;
- the controller including:
- a first sense amplifier coupled to the first bit line and a reference voltage, the first sense amplifier configured to compare voltage of the first bit line to the reference voltage;
- and
- a second sense amplifier coupled to the second bit line and the reference voltage, the second sense amplifier configured to compare voltage of the second bit line to the reference voltage.
A method of sensing memory cells in a memory circuit, comprising:
- charging a first word line to couple a memory cell to a first bit line based on timing of a first clock signal;
- sensing, by a first sense amplifier, a bit stored by the memory cell by comparing voltage of the first bit line to a reference voltage;
- charging a second word line to couple the memory cell to a second bit line based on timing of a second clock signal, the first and second clock signals generated in response to an external clock signal;
- and
- sensing, by a second sense amplifier, the bit stored by the memory cell by comparing voltage of the second bit line to the reference voltage.
Dependencies are inferred from the claim text.