Memory Power Rail Ramp-Up Control
AssigneeQUALCOMM Incorporated
InventorsSenpeng SHENG, Sunghyun PARK
Life of this patent
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Abstract
An integrated circuit is disclosed having a core power supply voltage rail supporting a core power supply voltage regulated by a core power supply voltage regulator. The integrated circuit also includes an always-on power supply voltage rail supporting an always-on power supply voltage regulated by an always-on power supply voltage regulator. A memory power supply voltage rail couples to an input power node of a memory in the integrated circuit to provide a memory power supply voltage to the memory. A multiplexer selectively couples the memory power supply voltage rail to either the always-on power supply voltage rail or to the core power supply voltage rail depending upon the operating mode of the memory.
Claims20
An integrated circuit, comprising:
- a core power supply voltage regulator configured to regulate a core power supply voltage coupled onto a core power supply voltage rail;
- an always-on power supply voltage regulator configured to regulate an always-on power supply voltage coupled onto an always-on power supply voltage rail;
- a memory including an input power node to receive an internal power supply voltage;
- and
- a multiplexer including a first transistor and a second transistor coupled in parallel between the always-on power supply voltage rail and the input power node and including at least a third transistor coupled between the core power supply voltage rail and the input power node, wherein the first transistor is larger than the second transistor.
A method of powering an integrated circuit, comprising:
- switching on a first transistor coupled between an always-on power supply voltage rail and a memory power supply voltage rail for a memory of the integrated circuit while a second transistor coupled between the always-on power supply voltage rail and the memory power supply voltage rail is maintained off to cause a memory power supply voltage carried by the memory power supply voltage rail to increase from ground towards an active level equaling an always-on power supply voltage during a first transition period from a sleep mode for the memory to an active mode for the memory;
- and
- switching on the first transistor simultaneously with the second transistor to cause the memory power supply voltage to increase from a retention level to the active level during a second transition period from a retention mode for the memory to the active mode, wherein the first transition period is longer than the second transition period, and the retention level is less than the active level.
A system, comprising:
- a memory power supply voltage rail;
- a memory configured to be powered by a memory power supply voltage from the memory power supply voltage rail;
- an always-on power supply voltage rail;
- an always-on power domain configured to be powered by an always-on power supply voltage from the always-on power supply voltage rail;
- and
- first means for coupling the always-on power supply voltage rail to the memory power supply voltage rail to cause the memory power supply voltage to increase at a first rate during a transition of the memory from a sleep mode in which the memory is powered down to an active mode in which the memory power supply voltage equals the always-on power supply voltage and to cause the memory power supply voltage to increase at a second rate during a transition of the memory from a retention mode for the memory to the active mode, wherein the second rate is greater than the first rate.
Dependencies are inferred from the claim text.