Patch to patch capacitor region in 3d-dram
AssigneeMicron Technology, Inc.
InventorsHiroki Fujisawa, Hiromasa Takeda
Life of this patent
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Abstract
A 3D memory device includes multiple memory patches each of which includes a 3D array of memory cells arranged at the intersection of word lines running in a first direction, local digit lines (LDLs) running in a second direction, and global digit lines (GDLs) running in a third directions. The GDLs are organized in pairs, with each pair coupled to a sense amplifier. In an example arrangement, an area between memory array patches may contain capacitors. For example, the capacitors may be for managing internal voltages of the memory device. In some embodiments, the memory cells directly adjacent to the capacitor region may be dummy memory cells to act as a buffer between active memory cells and the capacitors located in the capacitor region.
Claims20
An apparatus comprising:
- a plurality of memory patches arranged in matrix, each of the plurality of memory patches comprising a 3D memory array including a plurality of memory cells arranged at the intersection of a plurality of word lines and a plurality of local digit lines, wherein sets of the first plurality of local digit lines are coupled to a corresponding one of a plurality of global digit lines;
- and
- a plurality of 3D voltage compensation capacitor regions arranged in matrix, each of the plurality of 3D voltage compensation capacitor regions arranged between associated two of the plurality of memory patches and comprising a plurality of voltage compensation capacitors, wherein the plurality of voltage compensation capacitors have a same structure as capacitors of the plurality of memory cells.
An apparatus comprising:
- a 3D memory patch comprising a 3D memory array including a plurality of memory cells organized in a 3D grid at the intersection of a plurality of word lines extending in a first direction and a plurality of local digit lines extending in a second direction, wherein sets of the local digit lines are coupled by global digit lines extending in a third direction, the 3D memory array comprising a plurality of dummy memory cells positioned at the ends of the plurality of word lines;
- a plurality of sense amplifiers organized in at least one row extending along the first direction and positioned above the 3D memory array;
- and
- a plurality of capacitors extending along the second direction coupled to the plurality of sense amplifiers, wherein the plurality of capacitors is positioned adjacent to the plurality of dummy memory cells of the 3D memory array and below the plurality of sense amplifiers.
An apparatus comprising:
- a first die comprising:
- a plurality of 3D memory patches each comprising a 3D memory array including a plurality of memory cells arranged at the intersection of a plurality of word lines extending in a first direction and a plurality of local digit lines extending in a second direction orthogonal to the first direction, wherein sets of the plurality of local digit lines are coupled to one of a plurality of global digit lines extending in a third direction orthogonal to the first and the second direction and wherein the 3D memory patches are organized in a grid with rows extending in the first direction and columns extending in the second direction;
- and
- a capacitor region comprising a plurality of capacitors and coupled to the plurality of sense amplifiers, wherein the plurality of sense amplifier regions is positioned above the plurality of 3D memory arrays;
- and
- a second die comprising:
- a plurality of sense amplifier regions organized in a grid with rows extending in the first direction and columns extending in the third direction and comprising a plurality of sense amplifiers coupled to the plurality of global digit lines extending in the third direction.
Dependencies are inferred from the claim text.