Array organization in three-dimensional memory circuits

A method comprising:

• activating, in response to an activation to a memory array organized into N sections and each section having a row dimension K, a column dimension L, and a word line (WL) connected to L memory cells, the WL to generate an activated WL;
• routing data between a local input/output (LIO) line and a global input/output (GIO) line, and
• connecting the LIO line to a bit line (BL) by a column select (CS) signal, the BL being connected to one of the L memory cells and the one of the L memory cells being connected to the activated WL,
• wherein K, L, and N are positive integers.

A system comprising:

• a three-dimensional (3D) memory circuit comprising:
• a memory array configured to be organized into N sections, each section having a row dimension K, a column dimension L, and a word line (WL) connected to L memory cells;
• an activation circuit configured to activate, in response to an activation, the WL to generate an activated WL;
• and
• each section including a transfer circuit comprising:
• a data switch configured to route data between a local input/output (LIO) line and a global input/output (GIO) line, and
• a select switch configured to connect the LIO line to a bit line (BL) by a column select (CS) signal, the BL being connected to one of the L memory cells and the one of the L memory cells being connected to the activated WL,
• wherein K, L, and N are positive integers.