Display device and driving method thereof

A driving method of a display device, wherein the display device comprises a plurality of pixel units, each of the pixel units comprises a first transistor, a bootstrap capacitor, a second transistor, and a storage capacitor, a first terminal of the first transistor is coupled to a first gate signal line and a second terminal thereof is coupled to a first node, a first terminal of the bootstrap capacitor is coupled to a second gate signal line and a second terminal thereof is coupled to the first node, a first terminal of the second transistor is coupled to a data signal line to receive a data signal and a second terminal thereof is coupled to a second node, a control terminal of the second transistor is coupled to the first node, and the storage capacitor is coupled to the second node, the driving method comprising:

• in a first time period, boosting the first gate driving signal from a low voltage level to a high voltage level, so that the first transistor is switched from a conduction state to a turned-off state, and a first voltage of the first node is boosted to be close to a reference voltage;
• in a second time period after the first time period, boosting the second gate driving signal from the low voltage level to the high voltage level, the first transistor is in the turned-off state, and the first voltage of the first node is boosted from the reference voltage by a voltage value via the bootstrap capacitor, wherein the voltage value is substantially equal to a voltage difference between the low voltage level and the high voltage level, so that the second transistor is in a conduction state to write the data signal into the second node;
• in a third time period after the second time period, reducing the first gate driving signal from the high voltage level to the low voltage level, the first transistor returns to the conduction state, and the first voltage of the first node is reduced to the low voltage level via the first transistor in the conduction state;
• and
• in a fourth time period after the third time period, maintaining both the first gate drive signal and the second gate drive signal at the low voltage level, the first transistor is maintained in the conduction state, and the first voltage of the first node is stably maintained at the low voltage level.