Timing controller, display device including the same and operational method thereof
AssigneeLx Semicon Co., Ltd.
InventorJae Young HEO
Life of this patent
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Abstract
A timing controller includes a memory controller configured to receive image data through an input port and generate a memory control signal; a first memory on which a write/read operation is performed on the image data; a first data processor configured to perform a read operation on the data in the first memory, map it, and control packets; and a multiplexer, wherein the multiplexer is configured to control the first memory to be in sync with a second data processor configured to transmit a differential signal through an output port based on the memory control signal.
Claims10
A timing controller, comprising:
- a memory controller configured to receive image data through an input port and generate a memory control signal;
- a first memory on which a write/read operation is performed on the image data;
- a first data processor configured to perform a read operation on the data in the first memory, map it, and control packets;
- and
- a multiplexer,
- wherein the multiplexer is configured to control the first memory to be in sync with a second data processor configured to transmit a differential signal through an output port based on the memory control signal.
A timing controller, comprising:
- a memory controller configured to receive and transmit image data through an input port and generate a memory control signal;
- a data merger configured to receive the image data from the memory controller and merge them;
- a first memory on which a write/read operation is performed on the merged image data;
- a first data processor configured to perform a read operation on the data in the first memory and map it;
- a multiplexer configured to output the mapped data in order;
- and
- a second memory configured to output data output from the multiplexer in sync with a second data processor that transmits a differential signal to a source driver through a port.
A timing controller, comprising:
- a memory controller configured to receive image data through an input port and generate a memory control signal;
- a data merger configured to receive image data from the memory controller and merge them;
- a first memory on which a write/read operation is performed on the merged image data;
- a first processor configured to perform a read operation on the data in the first memory, map it, and control packets;
- and
- a multiplexer,
- wherein the multiplexer is configured to control the first memory to be in sync with a second processor that transmits a differential signal through an output port based on the memory control signal.
Dependencies are inferred from the claim text.