Optimization method, optimization apparatus, electronic device, storage medium and program product

An electronic device, comprising:

• a processor;
• and
• a memory, configured to store an executable instruction by the processor;
• wherein the processor is configured to perform a method for optimizing an arrangement of a resistor array, and the method comprises:
• creating a corresponding resistor array based on a conversion circuit of a digital-to-analog converter;
• establishing a mapping relationship between a layout resistor in the resistor array and a circuit resistor in the conversion circuit, wherein the layout resistor has a simulated resistance value, and the mapping relationship is used to determine a resistance value of the circuit resistor based on the layout resistor and the corresponding simulated resistance value;
• constructing a performance model of the digital-to-analog converter based on the mapping relationship;
• and
• performing iterative evolution on the mapping relationship based on the performance model until a target mapping relationship is obtained by evolution, wherein the target mapping relationship is used to determine a target arrangement of the layout resistor in the resistor array, to determine a target resistance value of the circuit resistor based on the target arrangement, and enable the performance model to output a target performance parameter based on the target resistance value.

A non-transitory computer-readable storage medium, wherein a computer program is stored on the non-transitory computer-readable storage medium, when the computer program is executed by a processor, a method for optimizing an arrangement of a resistor array is implemented, and the method comprises:

• creating a corresponding resistor array based on a conversion circuit of a digital-to-analog converter;
• establishing a mapping relationship between a layout resistor in the resistor array and a circuit resistor in the conversion circuit, wherein the layout resistor has a simulated resistance value, and the mapping relationship is used to determine a resistance value of the circuit resistor based on the layout resistor and the corresponding simulated resistance value;
• constructing a performance model of the digital-to-analog converter based on the mapping relationship;
• and
• performing iterative evolution on the mapping relationship based on the performance model until a target mapping relationship is obtained by evolution, wherein the target mapping relationship is used to determine a target arrangement of the layout resistor in the resistor array, to determine a target resistance value of the circuit resistor based on the target arrangement, and enable the performance model to output a target performance parameter based on the target resistance value.