Ddr frequency management in chiplet-based system

A method of operation for a chiplet-based system, comprising:

• accessing a first memory and a second memory through a unified memory mapping for an at least one first client in a primary chiplet die and for an at least one second client in a secondary chiplet die, wherein each at least one first client and each at least one second client accesses the first memory and the second memory according to a corresponding bandwidth;
• aggregating the corresponding bandwidth from each at least one first client and from each at least one second client to form an aggregated bandwidth;
• determining a memory clocking frequency that satisfies the aggregated bandwidth;
• and
• transitioning the first memory and the second memory to both operate according to the memory clocking frequency.

A chiplet-based system, comprising:

• a first memory;
• a second memory;
• a primary chiplet die and a secondary chiplet die configured to implement an at least one processor that operates according to an operating system and configured to access the first memory and the second memory through a unified memory mapping, wherein the primary chiplet die includes:
• an at least one first client implemented by the operating system and configured to access the first memory and the second memory through the unified memory mapping;
• a first memory controller;
• an aggregation entity configured to aggregate a memory access bandwidth for the at least one first client in the primary chiplet die and a memory access bandwidth for an at least one second client in the secondary chiplet die to form an aggregated bandwidth and configured to determine a memory clocking frequency for the first memory and the second memory that satisfies the aggregated bandwidth;
• and
• a first transition entity configured to command the first memory controller to transition the first memory to the memory clocking frequency.