Memory system and memory chip

A memory chip comprising:

• a plurality of memory banks;
• a first align circuit comprising a plurality of transceivers;
• data lines;
• a plurality set of data line sensing amplifiers coupled to the data lines and electrically coupled to a plurality set of bit line amplifiers, wherein each set of data line sensing amplifiers is corresponding to one memory bank of the plurality of memory banks and each set of data line sensing amplifiers are electrically connected to the plurality of transceivers through the data lines, a corresponding set of data line sensing amplifiers are configured to output a first plurality of data received from a corresponding memory bank to the plurality of transceivers which simultaneously transmit the first plurality of data in parallel to an I/O data bus during a read operation of the memory chip, and the I/O data bus are configured to output a second plurality of data to the plurality of transceivers which then simultaneously transmit the second plurality of data in parallel to the corresponding set of data line sensing amplifiers and then to the corresponding memory bank during a write operation of the memory chip, wherein the I/O data bus comprises a predetermined data width, and the plurality of transceivers are disposed between the I/O data bus and the plurality set of data line sensing amplifiers, wherein the corresponding memory bank is determined by a bank selection signal;
• and
• the I/O data bus coupled to pads of the memory chip, wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in the memory chip;
• wherein a data width of the first plurality of data outputted by the predetermined set of data line sensing amplifiers and received by the I/O data bus during the read operation is the same as the predetermined data width of the I/O data bus;
• and a data width of the second plurality of data outputted by the I/O data bus and received by the predetermined set of data line sensing amplifiers during the write operation is the same as the predetermined data width of the I/O data bus.

A memory chip comprising:

• a memory bank;
• an I/O data bus;
• a plurality of transceivers between a first plurality of data line sensing amplifiers and the I/O data bus, wherein the first plurality of data line sensing amplifiers are electrically coupled to a second plurality of bit line sensing amplifiers in the memory chip and configured to output a first plurality of data to the plurality of transceivers which then simultaneously transmit the first plurality of data in parallel to the I/O data bus during a read operation of the memory chip, the I/O data bus are configured to output a second plurality of data to the plurality of transceivers which then simultaneously transmit the second plurality of data in parallel to the first plurality of data line sensing amplifiers during a write operation of the memory chip, the I/O data bus comprises a predetermined data width;
• and
• the I/O data bus coupled to pads of the memory chip and configured to parallelly transmit the first plurality of data through the pads;
• wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in the memory chip;
• wherein a data width of the first plurality of data outputted by the first plurality of data line sensing amplifiers and received by the I/O data bus during the read operation is the same as the predetermined data width of the I/O data bus;
• and a data width of the second plurality of data outputted by the I/O data bus and received by the first plurality of data line sensing amplifiers during the write operation is the same as the predetermined data width of the I/O data bus;
• wherein the predetermined data width of the I/O data bus is determined by a control signal.