Memory controller, memory system, and control method of memory controller
AssigneeKioxia Corporation
InventorSohichiroh HOSODA
Life of this patent
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Abstract
According to one embodiment, a memory controller includes: a controller circuit configured to detect one or more streams including a plurality of windows of data to be transferred to a host device, the controller circuit being configured to control prefetching of the data; and a cache memory configured to store prefetched data, wherein the controller circuit is configured to detect the streams on a basis of a data size of each of one or more first windows among the plurality of windows and a successive number of the first windows in a first period.
Claims19
A memory controller comprising:
- a controller circuit configured to detect one or more streams including a plurality of windows of data to be transferred to a host device, the controller circuit being configured to control prefetching of the data;
- and
- a cache memory configured to store prefetched data,
- wherein the controller circuit is configured to detect the streams on a basis of a data size of each of one or more first windows among the plurality of windows and a successive number of the first windows in a first period.
A control method of a memory controller including a cache memory configured to store prefetched data, the method comprising:
- processing read access in response to a request from a host device;
- detecting one or more streams including a plurality of windows of data to be transferred to the host device in response to the read access on a basis of a data size of each of one or more first windows among the plurality of windows and a successive number of the first windows;
- and
- controlling prefetching of the data of the detected one or more streams using the cache memory.
Dependencies are inferred from the claim text.