Application programming interface to invalidate information
AssigneeNVIDIA Corporation
InventorsHarold Carter Edwards, Daniel Joseph Lustig, Gonzalo Brito Gadeschi, Subhasmita Chakraborty, Gokul Ramaswamy Hirisave Chandra Shekhara
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and techniques to cause information to be invalidated in a second cache location after information is stored in a first cache location. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be invalidated in a second cache location after information is stored in a first cache location.
Claims20
One or more processors, comprising circuitry to, in response to an application programming interface (API) call:
- responsive to determining that first cache information associated with a first processor is stored in a first cache location:
- invalidate second cache information associated with a second processor in a second cache location identified by a second identifier after the first cache information is stored in the first cache location;
- and
- prevent execution of subsequent instructions that access an address corresponding to the second cache location identified by the second identifier.
A system comprising one or more processors to, in response to an application programming interface (API) call:
- responsive to determining that first cache information associated with a first processor is stored in a first cache location:
- invalidate second cache information associated with a second processor in a second cache location identified by a second identifier after the first cache information is stored in the first cache location;
- and
- prevent execution of subsequent instructions that access an address corresponding to the second cache location identified by the second identifier.
A method comprising, in response to an application programming interface (API) call:
- responsive to determining that first cache information associated with a first processor is stored in a first cache location:
- invalidating second cache information associated with a second processor in a second cache location identified by a second identifier after the first cache information is stored in the first cache location;
- and
- preventing execution of subsequent instructions that access an address corresponding to the second cache location identified by the second identifier.
Dependencies are inferred from the claim text.