Performance state (pstate) control in a system-on-chip (soc)
AssigneeQUALCOMM Incorporated
InventorsXiuting Cheng MAN, Mohd Imran BEG, Hoan Huu NGUYEN, Nitin MAKHIJA
Life of this patent
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Abstract
In a processor system operating at a current performance state (Pstate), a processor may determine a fine-grained target Pstate, including target Pstate parameter values. Control circuitry may then transition through discrete Pstates, which may be stored in a table, from the current Pstate to a discrete Pstate closest to the fine-grained target Pstate. After reaching the discrete Pstate closest to the fine-grained target Pstate, the target Pstate parameter values may be provided to dynamic clock and voltage scaling (DCVS) or other circuitry associated with the processor system.
Claims20
A system for performance state (Pstate) control, comprising:
- Pstate storage circuitry configured to provide a plurality of discrete Pstates, each discrete Pstate including a plurality of discrete Pstate parameter values;
- and
- control circuitry configured to receive an indication of a target Pstate including a plurality of target Pstate parameter values, the control circuitry further configured to transition from a current Pstate to a discrete Pstate closest to the target Pstate from among a plurality of discrete Pstates, wherein the discrete Pstate parameter values differ from the target Pstate parameter values, the control circuitry further configured to provide the target Pstate parameter values to dynamic clock and voltage control circuitry associated with the processor system after transitioning to the discrete Pstate closest to the target Pstate.
A method for performance state (Pstate) control in a processor system, comprising:
- determining, by a processor, a target Pstate including a plurality of target Pstate parameter values;
- transitioning, by control circuitry, from a current Pstate to a discrete Pstate closest to the target Pstate from among a plurality of discrete Pstates, wherein the discrete Pstate includes discrete Pstate parameter values different from the target Pstate parameter values;
- and
- providing the target Pstate parameter values to dynamic clock and voltage control circuitry associated with the processor system after transitioning to the discrete Pstate closest to the target Pstate.
A system-on-chip (SoC), comprising:
- processor circuitry configured to determine a target performance state (Pstate) including a plurality of target Pstate parameter values;
- Pstate storage circuitry to provide a plurality of discrete Pstates, each discrete Pstate including a plurality of discrete Pstate parameter values;
- and
- control circuitry configured to receive from the processor circuitry an indication of the target Pstate and the plurality of target Pstate parameter values, the control circuitry further configured to transition from a current Pstate to a discrete Pstate closest to the target Pstate from among a plurality of discrete Pstates, wherein the discrete Pstate parameter values differ from the target Pstate parameter values, the control circuitry further configured to provide the target Pstate parameter values to dynamic clock and voltage control circuitry associated with the processor system after transitioning to the discrete Pstate closest to the target Pstate.
Dependencies are inferred from the claim text.