Failure fault tolerance in distributed memory systems
AssigneeMicron Technology, Inc.
InventorsCraig William Warner, Tony M. Brewer
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsCraig William Warner, Tony M. Brewer
Estimating the term…
Disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. In some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. In some examples, a memory processing unit (MPU) may be incorporated into the memory architecture to support these paired memory devices. The MPU may be placed between the host and a multi-planed memory fabric which connects to multi-ported CXL memory devices. In some examples, the MPU may also enable the use of alternative fabric links. That is, if a memory fabric link between the MPU and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.
A method for servicing read requests in a distributed memory system, the method comprising:
A memory processing unit for servicing read requests in a distributed memory system, the memory processing unit comprising:
A non-transitory machine-readable medium storing instructions for servicing read requests in a distributed memory system, the instructions, when executed by a memory processing unit connected across a host interface to a host and a memory fabric interface to a plurality of memory devices, the plurality of memory devices comprising a first memory device and a second memory device configured as a pair of memory devices, cause the memory processing unit to perform operations comprising:
Dependencies are inferred from the claim text.