Multiple-input fused multiply-and-accumulate unit for the logarithm number system

An accelerator device, comprising:

• a memory circuit;
• a processing core circuit comprising:
• a data memory storing a first operand formatted according to a logarithm number system format and a second operand formatted according to the logarithm number system format;
• and
• a multiply-accumulate (MAC) circuit configured to:
• access the first operand and the second operand according to a MAC instruction;
• generate an output value using the first operand and the second operand based on the MAC instruction, the output value formatted according to a floating-point format;
• and
• provide the output value for storage in the memory circuit.

A method, comprising:

• identifying, by a multiply-accumulate (MAC) circuit, a first logarithmic operand and a second logarithmic operand for a MAC operation;
• generating, by a first adder circuit of the MAC circuit, a sum of a first portion of the first logarithmic operand and a second portion of the second logarithmic operand;
• determining, by a lookup table of the MAC circuit, an output of an exponential function based on a fraction portion of the sum;
• and
• generating, by the MAC circuit, a floating-point output value using an integer portion of the sum and the output of the exponential function.