US 2026/0288226 A1 · DECREASING VOLTAGE TO A PROCESSOR CORE BASED ON THROTTLING AT THE PROCESSOR CORE

Decreasing voltage to a processor core based on throttling at the processor core

AssigneeInternatonal Business Machines Corporation

InventorsPradeep Bhadravati Parashurama, Tobias Webel, Phillip John Restle, Alper Buyuktosunoglu, Ramon Bertran Monfort, Aishwarya Rajiv Tadkase, Alejandro Alberto Cook Lobo, Sean Michael Carey, KARL EVAN SMOCK ANDERSON, Michael ROMAIN, Kevin P. Low, Rahman Abber Tahir

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Abstract

Provided are a computer implemented method, system, and processor for decreasing voltage to a processor core based on throttling at the processor core. A first sensor in a processor core generates a first output value based on an operational margin at the processor core. Execution at the processor core is throttled in response to the first output value satisfying a threshold condition. A second sensor in the processor core, operating at an offset margin from when the first sensor operates, generates a second output value based on the operational margin at the processor core. A determination is made of a voltage change based on the second output value. A voltage supplied to the processing unit is modified by the voltage change.

Claims25

Dependent claims

A computer implemented method for adjusting voltage at a processing unit, comprising:

generating, at a first sensor in a processor core, a first output value based on an operational margin at the processor core;
throttling execution at the processor core in response to the first output value satisfying a threshold condition;
generating, at a second sensor in the processor core operating at an offset margin from when the first sensor operates, a second output value based on the operational margin at the processor core;
determining a voltage change based on the second output value;
and
modifying voltage supplied to the processing unit by the voltage change.

3 more elements

A computer implemented method for adjusting voltage at a processing unit, comprising:

a first voltage control loop running at a first interval to determine whether a first interval throttling measurement, based on a number of times execution at a processor core was throttled during the first interval, exceeds a first throttling threshold;
increasing a voltage level a number of steps in response to determining that the first interval throttling measurement exceeds a throttling threshold;
a second voltage control loop running at a second interval, longer than the first interval, to determine whether a second interval throttling measurement, based on a number of times the processor core was throttled during the second interval, exceeds the throttling threshold;
and
changing a rate at which the voltage level is decreased in response to determining that the second interval throttling measurement exceeds the throttling threshold.

2 more elements

A processor, comprising:

a core including:
a first sensor to generate a first output value based on an operational margin at the core;
a second sensor, in the core operating at an offset margin from when the first sensor operates, generates a second output value based on the operational margin at the core;
and
a mitigation unit to throttle execution at the core in response to the first output value satisfying a threshold condition;
and
a power management engine implemented in the processor to perform:
determining a voltage change based on the second output value;
and
modifying voltage supplied to the core by the voltage change.

7 more elements

Dependencies are inferred from the claim text.