Memory bandwidth reduction for power savings
AssigneeApple Inc.
InventorsAlexander GENDLER, Daniel U. BECKER, Gregory S. MATHEWS
Life of this patent
Estimating the term…
Abstract
Memory bandwidth reduction for power savings is disclosed. A memory controller circuit is configured to conduct transactions with a memory circuit. The memory controller circuit includes an external interface circuit configured to receive a plurality of memory transactions, and a bandwidth reduction value. A control circuit of the memory controller circuit is configured to insert, in a particular memory transaction of the plurality of memory transactions having a plurality of slots, a plurality of idle slots using the bandwidth reduction value. A memory interface circuit in the memory controller circuit is configured to send the particular transaction to the memory circuit.
Claims20
A system comprising:
- a memory circuit;
- and
- a memory controller circuit configured to conduct transactions with the memory circuit, wherein the memory controller circuit includes a bandwidth controller circuit configured to:
- perform a plurality of transactions with the memory circuit;
- receive, via an interface of the memory controller, a bandwidth reduction value;
- and
- insert, in a particular transaction of the plurality of transactions having a plurality of slots, one or more idle slots, wherein the number of the one or more idle slots is dependent on the bandwidth reduction value.
A method comprising:
- performing, by a memory controller circuit, a plurality of transactions with a memory circuit;
- receiving, via an external interface of the memory controller circuit, a bandwidth reduction value;
- inserting, in a particular transaction of the plurality of transactions having a plurality of slots and using a bandwidth controller circuit of the memory controller, one or more idle slots, wherein a number of the one or more idle slots is dependent on the bandwidth reduction value;
- and
- sending, via a memory interface of the memory controller circuit, the particular transaction.
An apparatus, comprising:
- a memory controller circuit configured to conduct transactions with a memory circuit, the memory controller circuit comprising:
- an external interface circuit configured to receive a plurality of memory transactions, and a bandwidth reduction value;
- a control circuit configured to insert, in a particular memory transaction of the plurality of memory transactions having a plurality of slots, one or more idle slots using the bandwidth reduction value;
- and
- a memory interface circuit configured to send the particular memory transaction to the memory circuit.
Dependencies are inferred from the claim text.