Multiple-chip system and timing synchronization method

A timing synchronization method for a multiple-chip system, wherein the multiple-chip system comprises a plurality of chips, the plurality of chips comprises a first chip and at least one second chip, and the plurality of chips are connected to each other through a same input output bus, the timing synchronization method comprising:

• sequentially and respectively transmitting a plurality of detection patterns to the input output bus through the plurality of chips, wherein the plurality of detection patterns are sequentially transmitted through each of the at least one second chip first, and then the plurality of detection patterns are transmitted through the first chip;
• transmitting a synchronization pattern to the input output bus through the first chip;
• monitoring the synchronization pattern from the input output bus through each of the at least one second chip;
• and
• performing a given function through each of the plurality of chips based on the synchronization pattern.