Free Running Counter-Based Timer Memory Controller

A memory controller, comprising:

• a free running counter that maintains a count of a number of clock cycles remaining for a command to complete execution;
• and
• a timer logic coupled to the free running counter and including at least one timer module, the at least one timer module having a current snapshot input for receiving a current snapshot counter value from the free running counter, a timer value input for receiving a timer value associated with a new command and a timer expired output, wherein the current snapshot input receives a snapshot counter value from the free running counter and a timer value associated with fully executing a current command, and
• wherein the timer module includes a gated clock input that is coupled to a clock gate logic and that is configured to generate a first clock pulse to load the timer value to the timer module, a second clock pulse to compute when the timer module expires, and a third clock pulse when a pulse is generated at the timer expired output.

A method for controlling command-to-command timing in a memory controller, comprising:

• detecting, by the memory controller, a new command request;
• receiving, by a timer module of the memory controller, a current snapshot counter value from a free running counter, the current snapshot counter value indicating a first number of clock cycles for completing execution of a command being executed by a memory coupled to the memory controller;
• receiving, by the timer module of the memory controller, a timer value for a second number of clock cycles to complete execution of the new command request;
• summing, by the timer module of the memory controller, the first number of clock cycles and the second number of clock cycles as a timer snapshot value;
• comparing a current timer snapshot value to the timer snapshot value;
• and
• generating a timer expired pulse when the current timer snapshot value is equal to the timer snapshot value.