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US 2026/0288189 A1Published application
Voltage reference circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBei-Shing LIEN, Szu-Lin LIU
Life of this patent
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Abstract
A bandgap voltage reference circuit is provided. In one example, a cell includes a first device including a first plurality of MOSFETs connected in series The cell further includes a second device including a second plurality of MOSFETs connected in series. The second device connects in series with the first device. The second plurality of MOSFETs has a second Vt that is higher than the first Vt. The cell further includes a reference node connected between the first stack gate device and the second stack gate device.
Claims20
A cell, comprising:
- a first plurality of MOSFETs connected in series with each gate of the first plurality of MOSFETs connected to a first node, each MOSFET of the first plurality of MOSFETs having a first threshold voltage (Vt);
- a second plurality of MOSFETs connected in series, the second plurality of MOSFETs connected in series with the first plurality of MOSFETs, each MOSFET of the second plurality of MOSFETs having a second Vt that is higher than the first Vt;
- a reference node connected at a junction of the first plurality of MOSFETs and the second plurality of MOSFETs, the reference node being separate from the first node;
- and
- a trimming circuit including two or more inverters, the two or more inverters including a source/drain terminal connected to the first node, and at least one of the two or more inverters connected to the gates of the second plurality of MOSFETs.
2 more elements
A device, comprising:
- a voltage source;
- a voltage reference circuit coupled to the voltage source, the voltage reference circuit including a cell, the cell including:
- a plurality of MOSFETs connected in series with each gate of the plurality of MOSFETs connected to a first node, one or more of the plurality of MOSFETs having a first threshold voltage (Vt);
- a reference node connected at a junction of two or more of the plurality of MOSFETs, the reference node being separate from the first node;
- and
- a trimming circuit including two or more inverters, the two or more inverters including a source/drain terminal connected to the first node, and at least one of the two or more inverters connected to a gate of at least one of the plurality of MOSFETs.
3 more elements
A method, comprising:
- providing a current source;
- providing a first plurality of MOSFETs to form a first stack gate, the first plurality of MOSFETs connected to the current source at a first node;
- providing a second plurality of MOSFETs to form a second stack gate connected in series to the first stack gate;
- connecting a reference node between the first stack gate and the second stack gate;
- and
- outputing a voltage signal from the reference node.
3 more elements
Dependencies are inferred from the claim text.