Systems and methods for multi-channel parallel device testing

A system for parallel testing, the system comprising:

• one or more processors;
• a system clock;
• and
• a plurality of test channels coupled to the one or more processors, each of the plurality of test channels comprising one or more of:
• a pulse resource comprising a first branch and a second branch and a high speed switch coupled to the first branch and the second branch;
• or
• a measuring resource comprising a first configurable switch, a second configurable switch, and a direct digital synthesizer;
• a potential node coupled to a testing pin and one or more of the pulse resource or the measuring resource;
• wherein:
• the first branch comprises a pulse generator, a PGA, and a first branch switch;
• the second branch comprises circuitry for pulse current and voltage measurement and a second branch switch;
• any channel from the plurality of test channels is configurable as a high channel, low channel, pulse channel, or measurement channel, based on the configuration of corresponding first configurable switch and second configurable switch;
• and
• the one or more processor are configurable to perform operations comprise:
• configuring the direct digital synthesizers in test channels to generate test signals with unique frequency or phase;
• and
• simultaneously measure a group of the plurality of test channels by configuring corresponding direct digital synthesizer to generate test signals, the test signals having a phase and frequency determined based on the system clock.

A system of parametric multi-channel testing, the system comprising:

• a plurality of test channels, the plurality of test channels comprising:
• a resource comprising one or more of a pulse resource and a measuring resource;
• a channel processing circuit;
• a mode switch coupled to one or more of the pulse resource, the measuring resource, and the processing circuit;
• and
• a node coupled to the mode switch and a testing pin;
• and
• wherein:
• the pulse resource comprises a high speed switch and a programmable-gain amplifier;
• the measurement resource comprises a first configurable switch, a second configurable switch, and a direct digital synthesizer;
• the plurality of test channels are configurable via a processor to operate as any of a high channel, a low channel, pulse channel, or a measurement channel based on an arrangement of the first configurable switch, the second configurable switch, and the mode switch;
• the direct digital synthesizers in test channels are configured to generate test signals with unique frequency or phase and are calibrated with respect to a system clock;
• and
• the processing circuit is configured to perform operations comprising at least one of:
• converting analog measurements to digital measurements or transforming signals from time domain into frequency domain, or transmitting digital data to a processor.