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US 2026/0287654 A1Published application
Memory devices and memory systems outputting codes
AssigneeSK hynix Inc.
InventorsMin Kyu MOON, Kyung Jun CHO
Life of this patent
Estimating the term…
Abstract
The present disclosure provides a memory device including a base die, and a plurality of core dies stacked over the base die and connected to the base die using a plurality of through vias and a plurality of bump pads. The base die outputs a test code as a read code through an output pad in synchronization with a first edge of a test clock signal in a normal mode and outputs the test code as the read code through the output pad in synchronization with the first edge and a second edge of the test clock signal in an acceleration mode.
Claims20
A memory device comprising:
- a base die;
- and
- a plurality of core dies stacked over the base die and connected to the base die using a plurality of through vias and a plurality of bump pads,
- wherein the base die is configured to output a test code as a read code through an output pad in synchronization with a first edge of a test clock signal in a normal mode and configured to output the test code as the read code through the output pad in synchronization with the first edge and a second edge of the test clock signal in an acceleration mode.
1 more element
A memory system comprising:
- an interposer stacked over a substrate;
- and
- a memory device and a processor stacked over the interposer and connected to each other through wires formed in the interposer,
- wherein the memory device comprises a base die and a plurality of core dies stacked over the interposer,
- wherein the base die and the plurality of core dies are connected to each other using a plurality of through vias and a plurality of bump pads, and
- wherein the base die is configured to output a test code as a read code through an output pad in synchronization with a first edge of a test clock signal in a normal mode and configured to output the test code as the read code through the output pad in synchronization with the first edge and a second edge of the test clock signal in an acceleration mode.
3 more elements
Dependencies are inferred from the claim text.