Under-Bump-Metallization Structure and Redistribution Layer Design for Integrated Fan-Out Package with Integrated Passive Device

A semiconductor package comprising:

• an integrated passive device (IPD) comprising:
• passive devices on a substrate;
• an interconnect structure over and electrically coupled to the passive devices, wherein a top metallization layer of the interconnect structure comprises first metal patterns and second metal patterns interleaved with the first metal patterns, the first metal patterns and the second metal patterns configured to be coupled to a power supply and an electrical ground, respectively;
• a first under bump metallization (UBM) structure over the interconnect structure, and
• wherein the first UBM structure comprises first metal strips and second metal strips interleaved with the first metal strips, the first metal strips electrically coupled to respective ones of the first metal patterns, and the second metal strips electrically coupled to respective ones of the second metal patterns;
• an integrated fan-out (InFO) package comprising:
• a die surrounded by a molding material;
• a redistribution structure on the molding material and electrically coupled to the die, wherein a top redistribution layer of the redistribution structure comprises third metal patterns and fourth metal patterns interleaved with the third metal patterns, wherein the third metal patterns and the fourth metal patterns are electrically coupled to the first metal patterns and the second metal patterns, respectively;
• and
• a second UBM structure electrically coupled to the redistribution structure;
• and a solder region bonding the first UBM structure to the second UBM structure.

A semiconductor structure comprising:

• a first package including:
• a semiconductor die having a front side and a back side;
• a molding material laterally surrounding the semiconductor die;
• a front-side redistribution structure at the front side of the semiconductor die ;
• a backside redistribution structure at the back side of the semiconductor die;
• through-mold conductive pillars extending through the molding material and electrically connecting the front-side redistribution structure to the backside redistribution structure;
• and
• a first comb-shaped pattern at a side of the front-side redistribution structure facing away from the semiconductor die;
• a second package joined to the backside redistribution structure of the first package through conductive joints, the second package including:
• one or more memory dies attached to a package substrate;
• and
• an integrated passive device attached to the first package and having a plurality of capacitors at a semiconductor substrate, an interconnect structure above the plurality of capacitors, the interconnect structure parallel-connecting the plurality of capacitors, wherein a topmost metallization layer of the interconnect structure comprises power patterns and ground patterns alternately disposed;
• and
• a second comb-shaped pattern electrically coupled to the topmost metallization layer;
• and
• a solder region joining the second comb-shaped pattern of the integrated passive device to the first comb-shaped pattern of the first package.