Semiconductor packge

A semiconductor package, comprising:

• a first redistribution substrate;
• a chip stacked structure including a first sub-stack and a second sub-stack arranged on the first sub-stack, wherein the first sub-stack is arranged on the first redistribution substrate and includes a plurality of semiconductor chips stacked on the first sub-stack and the second sub-stack is arranged on the first sub-stack and includes a plurality of semiconductor chips stacked on the second sub-stack;
• a second redistribution substrate arranged on the chip stacked structure;
• a first sub-stack vertical wiring unit configured to connect each of the semiconductor chips constituting the first sub-stack except for the semiconductor chip at a lowermost end of the semiconductor chips to the first redistribution substrate and including vertical wires configured to extend to an upper surface of the first redistribution substrate in a vertical direction;
• a second sub-stack vertical wiring unit configured to connect each of the semiconductor chips constituting the second sub-stack except for the semiconductor chip at an uppermost end of the semiconductor chips to the second redistribution substrate and including vertical wires configured to extend to a lower surface of the second redistribution substrate in the vertical direction;
• and
• a first sealing material sealing the chip stacked structure, the first sub-stack vertical wiring unit, and the second sub-stack vertical wiring unit between the first redistribution substrate and the second redistribution substrate,
• wherein a lower surface of the semiconductor chip at a lowermost end of the semiconductor chips constituting the first sub-stack is coplanar with the upper surface of the first redistribution substrate, and an upper surface of the semiconductor chip at an uppermost end of the semiconductor chips constituting the second sub-stack is coplanar with a lower surface of the second redistribution substrate.

A semiconductor package comprising:

• a first redistribution substrate;
• an external connection terminal arranged under a lower surface of the first redistribution substrate;
• a chip stacked structure including a first sub-stack and a second sub-stack, which are vertically stacked on the first redistribution substrate;
• a second redistribution substrate arranged on the chip stacked structure;
• a first sub-stack vertical wiring unit configured to connect the first sub-stack to the first redistribution substrate;
• a second sub-stack vertical wiring unit configured to connect the second sub-stack to the second redistribution substrate;
• a first vertical wiring unit configured to be electrically and vertically connected between the first redistribution substrate and the second redistribution substrate;
• and
• a first sealing material sealing the chip stacked structure, the first sub-stack vertical wiring unit, and the second sub-stack vertical wiring unit between the first redistribution substrate and the second redistribution substrate,
• wherein the first sub-stack comprises a first semiconductor chip arranged apart from the first redistribution substrate on the first redistribution substrate so that an active surface thereof faces toward the first redistribution substrate and a second semiconductor chip stacked shifted on the first semiconductor chip in a first horizontal direction so that an active surface thereof faces toward the first redistribution substrate,
• wherein the second sub-stack comprises a third semiconductor chip stacked so that an active surface thereof faces toward the second redistribution substrate and aligned with the first semiconductor chip, and a fourth semiconductor chip stacked so that an active surface thereof faces toward the second redistribution substrate on the third semiconductor chip and aligned to the second semiconductor chip,
• wherein the first sub-stack vertical wiring unit comprises a first sub-stack contact unit in contact with a first lower substrate pad arranged on a lower surface of each of the first semiconductor chip and the second semiconductor chip and a first sub-stack extension unit extending between the first sub-stack contact unit and the first redistribution substrate, and
• wherein the second sub-stack vertical wiring unit comprises a second sub-stack contact unit in contact with a second upper substrate pad arranged on an upper surface of each of the third semiconductor chip and the fourth semiconductor chip and a second sub-stack extension unit extending between the second sub-stack contact unit and the second redistribution substrate.