Method of forming a chiplet device prototype

A method, comprising:

• forming a first wafer including a first IC device including (a) first function circuitry located in a partial footprint of the first IC device and (b) a plurality of first bond pads located outside the partial footprint of the first IC device;
• forming a second wafer including a second IC device including (a) second function circuitry located in a partial footprint of the second IC device and (b) a plurality of second bond pads and located outside the partial footprint of the second IC device;
• forming (a) a plurality of first relocated bond pads corresponding with respective ones of the first bond pads and (b) first redistribution layer (RDL) structures on the first IC device and within the partial footprint of the first IC device, the first RDL structures connecting respective first relocated bond pads with corresponding first bond pads;
• forming (a) a plurality of second relocated bond pads corresponding with respective ones of the second bond pads and (b) second RDL structures on the second IC device and within the partial footprint of the second IC device, the second RDL structures connecting respective second relocated bond pads with corresponding second bond pads;
• dicing the first IC device from the first wafer to provide a diced first IC device;
• dicing the second IC device from the second wafer to provide a diced second IC device;
• arranging the diced first IC device adjacent the diced second IC device;
• and
• forming RDL bond pad interconnection structures to connect respective first relocated bond pads formed on the first IC device with respective second relocated bond pads formed on the second IC device, to thereby connect the first function circuitry on the first IC device with the second function circuitry on the second IC device.

An integrated circuit (IC) device, comprising:

• a first IC device including:
• first function circuitry located in a partial footprint of the first IC device;
• a plurality of first bond pads;
• and
• a first IC device redistribution layer (RDL) formed above the first function circuitry, the first IC device RDL including a plurality of first relocated bond pads and first bond pad connection structures formed within the partial footprint of the first IC device, wherein the first relocated bond pads have different locations relative to corresponding first bond pads, and wherein the first bond pad connection structures connect respective first relocated bond pads with corresponding ones of the first bond pads;
• a second IC device arranged adjacent the first IC device and including:
• second function circuitry located in a partial footprint of the second IC device;
• a plurality of second bond pads;
• and
• a second IC device redistribution layer (RDL) formed above the second function circuitry, the second IC device RDL including a plurality of second relocated bond pads and second bond pad connection structures formed within the partial footprint of the second IC device, wherein the second relocated bond pads have different locations relative to corresponding second bond pads, and wherein the second bond pad connection structures connect respective second relocated bond pads with corresponding ones of the second bond pads;
• a plurality of RDL bond pad interconnection structures formed in an RDL layer above the first IC device RDL layer and the second IC device RDL layer, the plurality of RDL bond pad interconnection structures connect respective first relocated bond pads formed on the first IC device with respective second relocated bond pads formed on the second IC device, thereby connecting the first function circuitry on the first IC device with the second function circuitry on the second IC device.