Semiconductor module and method for manufacturing semiconductor module

A semiconductor module in which a semiconductor device of a chip-size package type is face-down mounted above a mounting substrate, the semiconductor device including one or more vertical metal oxide semiconductor (MOS) transistors,

• wherein the semiconductor device includes:
• a semiconductor layer;
• a metal layer stacked on the semiconductor layer and in contact with a lower surface of the semiconductor layer;
• and
• n pads disposed in an upper surface of the semiconductor device, n being an integer of 2 or more,
• the semiconductor device is curved projectingly in a direction in which a center of the semiconductor device in a plan view of the semiconductor device is away from the mounting substrate,
• the mounting substrate includes n lands corresponding one-to-one to the n pads,
• each of the n pads is joined by solder bonding material to one of the n lands corresponding to the pad, and
• when with use of n mutually distinct values of k, where k is an integer between 1 and n, inclusive, each of the n pads is denoted as a k-th pad, each of the n lands corresponding to the n pads indexed by k is denoted as a k-th land, an area of each of the n pads indexed by k in the plan view of the semiconductor device is denoted by P(k), an area of each of the n lands indexed by k in a plan view of the mounting substrate is denoted by L(k), and a distance in the plan view of the semiconductor device from the center of the semiconductor device to a center of each of the n pads indexed by k is denoted by D(k),
• the n pads indexed by k and the n lands indexed by k include a k1-th pad and a k1-th land satisfying P(k1)=L(k1), the k1-th pad and the k1-th land being identical in shape in the plan view of the semiconductor device, and
• the n pads indexed by k and the n lands indexed by k include a k3-th pad and a k3-th land satisfying D(k1)>D(k3) and P(k3)/L(k3)>1.

A method for manufacturing a semiconductor module by face-down mounting a semiconductor device of a chip-size package type above a mounting substrate using a stencil, the semiconductor device including one or more vertical metal oxide semiconductor (MOS) transistors,

• wherein the semiconductor device includes:
• a semiconductor layer;
• a metal layer stacked on the semiconductor layer and in contact with a lower surface of the semiconductor layer;
• and
• n pads disposed in an upper surface of the semiconductor device, n being an integer of 2 or more,
• the semiconductor device is curved projectingly in a direction in which a center of the semiconductor device in a plan view of the semiconductor device is away from the mounting substrate,
• the mounting substrate includes n lands corresponding one-to-one to the n pads,
• the stencil includes n apertures corresponding one-to-one to the n pads,
• each of the n apertures is an aperture for providing, above one of the n lands corresponding to the aperture, solder bonding material for joining one of the n pads corresponding to the aperture and the one of the n lands,
• when Pa denotes an area of a closest pad among the n pads in the plan view of the semiconductor device, La denotes an area of a closest land among the n lands in a plan view of the mounting substrate, and Sa denotes an area of a closest aperture among the n apertures in a plan view of the stencil, the closest pad being closest to the center of the semiconductor device in the plan view of the semiconductor device, the closest land corresponding to the closest pad, the closest aperture corresponding to the closest pad,
• Sa is larger than each of Pa and La, and
• the method comprises:
• a first process of providing the solder bonding material above each of the n lands by using the stencil;
• and
• a second process of joining each of the n pads to one land corresponding to the pad among the n lands by performing reflow processing, using the solder bonding material provided above the one land by performing the first process.