Semiconductor package and electronic system including the same

A semiconductor package comprising:

• a package substrate including a substrate base, a plurality of upper surface connection pads disposed on an upper surface of the substrate base, a plurality of lower surface connection pads disposed on a lower surface of the substrate base and electrically connected to the plurality of corresponding upper surface connection pads, an upper solder resist layer covering the upper surface of the substrate base, and a lower solder resist layer covering the lower surface of the substrate base;
• at least one semiconductor chip attached onto the package substrate and electrically connected to the plurality of upper surface connection pads;
• a plurality of package connection terminals attached onto the plurality of lower surface connection pads;
• a molding layer covering the upper surface of the package substrate and surrounding the at least one semiconductor chip;
• and
• an electromagnetic wave shielding layer covering the package substrate and the molding layer,
• wherein a lower surface of the lower solder resist layer has a first lower surface region having a first arithmetic average roughness and spaced apart from the plurality of package connection terminals, and a second lower surface region having a second arithmetic average roughness that is less than the first arithmetic average roughness,
• a first length, which is a shortest distance between an edge of the package substrate and the plurality of package connection terminals in a first horizontal direction, is less than a second length, which is a shortest distance between the edge of the package substrate and the plurality of package connection terminals in a second horizontal direction orthogonal to the first horizontal direction, and
• the first lower surface region has a horizontal width greater than or equal to ½ of the first length and is disposed along the edge of the package substrate.

An electronic system comprising:

• a package substrate including a substrate base, a plurality of upper surface connection pads disposed on an upper surface of the substrate base, a plurality of lower surface connection pads disposed on a lower surface of the substrate base and electrically connected to the plurality of corresponding upper surface connection pads, an upper solder resist layer covering the upper surface of the substrate base, and a lower solder resist layer covering the lower surface of the substrate base;
• at least one semiconductor chip attached onto the package substrate and electrically connected to the plurality of upper surface connection pads;
• a plurality of package connection terminals attached onto the plurality of lower surface connection pads;
• a molding layer covering the upper surface of the package substrate and surrounding the at least one semiconductor chip;
• an electromagnetic wave shielding layer covering the package substrate and the molding layer;
• a system substrate including a system substrate base, a plurality of upper system connection pads disposed on an upper surface of the system substrate base, the plurality of package connection terminals being attached onto the plurality of upper system connection pads, an upper system solder resist layer covering the upper surface of the system substrate base, and a lower system solder resist layer covering a lower surface of the system substrate base;
• and
• a system underfill layer surrounding the plurality of package connection terminals and disposed between the package substrate and the system substrate,
• wherein a lower surface of the lower solder resist layer has a first lower surface region having a first arithmetic average roughness and a second lower surface region having a second arithmetic average roughness that is less than the first arithmetic average roughness,
• the first lower surface region is spaced apart from the plurality of package connection terminals and disposed along an edge of the package substrate, and
• a part of an upper surface of the system underfill layer is in contact with the first lower surface region.