Semiconductor package

A fan-out semiconductor package comprising:

• a first redistribution structure;
• a second redistribution structure on the first redistribution structure;
• a plurality of conductive vias between the first redistribution structure and the second redistribution structure, the plurality of conductive vias electrically connecting the first redistribution structure and the second redistribution structure;
• a first chip structure on the first redistribution structure in a first fan-in region in a plan view;
• a second chip structure on the first redistribution structure in a second fan-in region spaced apart from the first fan-in region in the plan view;
• and
• an encapsulation layer on the first chip structure and the second chip structure,
• wherein the first fan-in region and the second fan-in region are each spaced apart from the plurality of conductive vias,
• wherein the first chip structure comprises a first chip on the first redistribution structure, a second chip on the first chip, and a first chip wiring structure on the second chip,
• wherein the second chip structure comprises a third chip on the first redistribution structure, a fourth chip on the third chip, and a second chip wiring structure on the fourth chip, and
• wherein the second redistribution structure comprises a plurality of second redistribution vias, a second redistribution layer, and a redistribution insulating layer.

A fan-out semiconductor package comprising:

• a first redistribution structure;
• a second redistribution structure on the first redistribution structure, the second redistribution structure comprising a plurality of second redistribution vias, a second redistribution layer, and a redistribution insulating layer;
• a plurality of conductive vias between the first redistribution structure and the second redistribution structure, the plurality of conductive vias electrically connecting the first redistribution structure and the second redistribution structure;
• a first chip structure on the first redistribution structure in a first fan-in region in a plan view;
• a second chip structure on the first redistribution structure in a second fan-in region spaced apart from the first fan-in region in the plan view;
• and
• an encapsulation layer on the first chip structure and the second chip structure,
• wherein the first chip structure comprises a first chip on the first redistribution structure, a second chip on the first chip, a bonding layer between the first chip and the second chip, and a chip wiring structure on the second chip,
• wherein the second redistribution structure comprises a seed layer on a bottom surface of the second redistribution layer and bottom surfaces of the plurality of second redistribution vias,
• wherein the chip wiring structure comprises a chip wiring element and a chip wiring pad,
• wherein the seed layer contacts the chip wiring pad and at least some of the plurality of conductive vias,
• wherein the seed layer comprises a titanium-copper alloy,
• wherein the first fan-in region and the second fan-in region are each spaced apart from the plurality of conductive vias, and
• wherein side surfaces of the first chip and side surfaces of the second chip contact the encapsulation layer.