US 2026/0282937 A1 · SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor package according to embodiments includes a first semiconductor die and a second semiconductor die on the first semiconductor die, the first semiconductor die comprising: a first die base; a first bonding dielectric layer on a back side of the first die base; a plurality of first key patterns penetrating the first bonding dielectric layer; and a plurality of second key patterns penetrating the first bonding dielectric layer, each second key pattern surrounding a corresponding first key pattern of the plurality of first key patterns, the second semiconductor die comprising: a second die base; a second bonding dielectric layer disposed on a front side of the second die base and bonded to the first bonding dielectric layer; a plurality of third key patterns penetrating the second bonding dielectric layer, each third key pattern bonding to a corresponding first key pattern of the plurality of first key patterns; and a plurality of fourth key patterns penetrating the second bonding dielectric layer, each fourth key pattern surrounding a corresponding third key pattern of the plurality of third key patterns and bonding to a corresponding second key pattern of the plurality of second key patterns, wherein: each of the plurality of first key patterns has a first width in a horizontal direction, each of the plurality of second key patterns has a second width in the horizontal direction, each of the plurality of third key patterns has a third width in the horizontal direction, each of the plurality of fourth key patterns has a fourth width in the horizontal direction, the first width is smaller than the third width, and the second width is larger than the fourth width.

Claims20

Dependent claims

A semiconductor package comprising:

a first semiconductor die and a second semiconductor die on the first semiconductor die,
the first semiconductor die comprising:
a first die base;
a first bonding dielectric layer on a back side of the first die base;
a plurality of first key patterns penetrating the first bonding dielectric layer;
and
a plurality of second key patterns penetrating the first bonding dielectric layer, each second key pattern surrounding a corresponding first key pattern of the plurality of first key patterns,
the second semiconductor die comprising:
a second die base;
a second bonding dielectric layer disposed on a front side of the second die base and bonded to the first bonding dielectric layer;
a plurality of third key patterns penetrating the second bonding dielectric layer, each third key pattern bonding to a corresponding first key pattern of the plurality of first key patterns;
and
a plurality of fourth key patterns penetrating the second bonding dielectric layer, each fourth key pattern surrounding a corresponding third key pattern of the plurality of third key patterns and bonding to a corresponding second key pattern of the plurality of second key patterns,
wherein:
each of the plurality of first key patterns has a first width in a horizontal direction,
each of the plurality of second key patterns has a second width in the horizontal direction,
each of the plurality of third key patterns has a third width in the horizontal direction,
each of the plurality of fourth key patterns has a fourth width in the horizontal direction,
the first width is smaller than the third width, and
the second width is larger than the fourth width.

17 more elements

A semiconductor package comprising:

a first semiconductor die comprising a first die base and a first bonding layer on a back side of the first die base;
and
a second semiconductor die comprising a second die base and a second bonding layer on a front side of the second die base,
wherein the first bonding layer includes:
a first dielectric layer;
a plurality of first bonding pads penetrating the first dielectric layer;
and
a plurality of first key pattern groups penetrating the first dielectric layer,
wherein each of the plurality of first key pattern groups includes a first inner key pattern and a first outer key pattern around the first inner key pattern, and
the second bonding layer includes:
a second dielectric layer bonded to the first dielectric layer;
a plurality of second bonding pads penetrating the second dielectric layer, wherein each of the plurality of second bonding pads is bonded to a corresponding first bonding pad of the plurality of first bonding pads;
and
a plurality of second key pattern groups penetrating the second dielectric layer,
wherein each of the plurality of second key pattern groups includes a second inner key pattern and a second outer key pattern around the second inner key pattern, and the second inner key pattern is bonded to the corresponding first inner key pattern, and the second outer key pattern is bonded to the corresponding first outer key pattern, and
wherein a width in a horizontal direction of the first inner key pattern is smaller than a width in the horizontal direction of the second inner key pattern, and a width in the horizontal direction of the first outer key pattern is larger than a width in the horizontal direction of the second outer key pattern.

13 more elements

A semiconductor package comprising:

a semiconductor stack in which a plurality of semiconductor dies are sequentially stacked from the bottom,
wherein each of the plurality of semiconductor dies comprises:
a die base including a front side and a back side opposite the front side;
a device layer on the front side;
a wiring layer on the device layer;
and
at least one of a front side bonding layer on the wiring layer and a back side bonding layer on the back side,
wherein each of the front side bonding layer and the back side bonding layer includes a dielectric layer and a plurality of key pattern groups penetrating the dielectric layer, and
wherein each of the plurality of key pattern groups includes an inner key pattern and an outer key pattern surrounding the inner key pattern,
wherein:
the dielectric layer of back side bonding layer of each of the plurality of semiconductor dies is bonded to the dielectric layer of the front side bonding layer of an adjacent semiconductor die,
the inner key pattern of back side bonding layer of each of the plurality of semiconductor dies is bonded to the inner key pattern of the front side bonding layer of an adjacent semiconductor die,
the outer key pattern of back side bonding layer of each of the plurality of semiconductor dies is bonded to the outer key pattern of the front side bonding layer of an adjacent semiconductor die,
the inner key pattern of back side bonding layer of each of the plurality of semiconductor dies has a first width in a horizontal direction,
the outer key pattern of back side bonding layer of each of the plurality of semiconductor dies has a second width in the horizontal direction,
the inner key pattern of front side bonding layer of each of the plurality of semiconductor dies has a third width in the horizontal direction,
the outer key pattern of front side bonding layer of each of the plurality of semiconductor dies has a fourth width in the horizontal direction,
the first width is less than the third width, and
the second width is greater than the fourth width.

16 more elements

Dependencies are inferred from the claim text.

Semiconductor package and method for manufacturing the same

Life of this patent

Semiconductor package and method for manufacturing the same

Life of this patent

Abstract

Claims20