Memory circuit, semiconductor device, and electronic device
AssigneeSony Semiconductor Solutions Corporation
InventorYASUO KANDA
Life of this patent
Estimating the term…
Abstract
To achieve miniaturization of a memory circuit. The memory circuit includes a memory cell and an applied voltage adjustment unit. The memory cell included in the memory circuit is equipped with: a resistive element; and a cell transistor that is connected to one end of the resistive element and controls a voltage to be applied to the resistive element. The applied voltage adjustment unit included in the memory circuit adjusts an impedance of an impedance element connected in series to a power supply line that supplies power to the memory cell so as to adjust the voltage to be applied to the memory cell.
Claims12
A memory circuit comprising:
- a memory cell, the memory cell being equipped with a resistive element and a cell transistor, the cell transistor being connected to one end of the resistive element and configured to control a voltage to be applied to the resistive element;
- and
- an applied voltage adjustment unit, the applied voltage adjustment unit configured to adjust impedance of an impedance element connected in series to a power supply line that supplies power to the memory cell so as to adjust a voltage to be applied to the memory cell.
A semiconductor device comprising:
- a memory circuit;
- and
- a control unit that controls the memory circuit, the memory circuit including:
- a memory cell being equipped with a resistive element and a cell transistor, the cell transistor being connected to one end of the resistive element and configured to control a voltage to be applied to the resistive element;
- and
- an applied voltage adjustment unit, the applied voltage adjustment unit configured to adjust impedance of an impedance element connected in series to a power supply line that supplies power to the memory cell so as to adjust a voltage to be applied to the memory cell.
An electronic device comprising:
- a memory device;
- and
- a host processor configured to perform data communication with the memory device,
- the memory device including:
- a memory circuit;
- and
- a control unit that controls the memory circuit, the memory circuit including:
- a memory cell being equipped with a resistive element and a cell transistor, the cell transistor being connected to one end of the resistive element and configured to control a voltage to be applied to the resistive element;
- and
- an applied voltage adjustment unit, the applied voltage adjustment unit configured to adjust impedance of an impedance element connected in series to a power supply line that supplies power to the memory cell so as to adjust a voltage to be applied to the memory cell.
Dependencies are inferred from the claim text.