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US 2026/0282879 A1Published application
Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorToshio HINO
Life of this patent
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Abstract
In a semiconductor integrated circuit device having clock buffer cells, back-side interconnects are provided. The clock buffer cells each include: a first signal line serving as an input terminal, formed in an interconnect layer located on the front side of a transistor; and a second signal line serving as the input terminal, formed in an interconnect layer located on the back side of the transistor. The line width of the second signal line is larger than the line width of the first signal line.
Claims8
A semiconductor integrated circuit device, comprising:
- a clock buffer cell having an input terminal and an output terminal, the clock buffer cell being a standard cell for transmitting a clock signal,
- wherein
- the clock buffer cell includes
- a transistor,
- a first signal line serving as the input terminal, formed in a first interconnect layer located on a front side of the transistor, and
- a second signal line serving as the input terminal, formed in a second interconnect layer located on a back side of the transistor, and
- a line width of the second signal line is larger than a line width of the first signal line.
4 more elements
A semiconductor integrated circuit device, comprising:
- a clock buffer cell having an input terminal and an output terminal, the clock buffer cell being a standard cell for transmitting a clock signal,
- wherein
- the clock buffer cell includes
- a transistor,
- a first signal line serving as the output terminal, formed in a first interconnect layer located on a front side of the transistor, and
- a second signal line serving as the output terminal, formed in a second interconnect layer located on a back side of the transistor, and
- a line width of the second signal line is larger than a line width of the first signal line.
4 more elements
Dependencies are inferred from the claim text.