Semiconductor structure and method of formation

A method of forming an integrated chip, comprising:

• forming a lower interconnect within a lower ILD layer formed on a substrate;
• forming one or more intermediate interconnects within one or more intermediate ILD layers formed on the substrate;
• etching the one or more intermediate ILD layers to form an opening extending through the one or more intermediate ILD layers;
• introducing an etchant into the opening to etch the one or more intermediate ILD layers to form a via opening, the via opening exposing an upper surface of the lower interconnect and a sidewall of the one or more intermediate interconnects;
• and
• forming a via comprising a conductive material within the via opening.

A method of forming an integrated chip, comprising:

• fabricating a lower interconnect layer within a lower ILD layer formed on a substrate;
• fabricating a first intermediate interconnect segment and a second intermediate interconnect segment within an intermediate ILD layer formed over the lower ILD layer;
• etching the intermediate ILD layer to form an opening extending through the intermediate ILD layer and between the first intermediate interconnect segment and the second intermediate interconnect segment;
• increasing a width of the opening to form a via opening, the via opening exposing an upper surface of the lower interconnect layer and sidewalls of the first intermediate interconnect segment and the second intermediate interconnect segment;
• and
• depositing a conductive material within the via opening.