US 2026/0282870 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a first semiconductor structure including a first semiconductor substrate and a first semiconductor element layer on a first surface of the first semiconductor substrate, and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including a second semiconductor substrate and a second semiconductor element layer on a second surface of the second semiconductor substrate. The second semiconductor structure includes a first via structure vertically penetrating the second semiconductor substrate and connected to the second semiconductor element layer, the first via structure is exposed on a third surface of the second semiconductor substrate, and a passivation layer covering the third surface. The second semiconductor substrate includes a recess region provided on the third surface and surrounding the first via structure. The passivation layer includes a protrusion fills the recess region. The passivation layer is in contact with the first via structure.

Claims20

Dependent claims

A semiconductor memory device comprising:

a first semiconductor structure including a first semiconductor substrate and a first semiconductor element layer on a first surface of the first semiconductor substrate;
and
a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including a second semiconductor substrate and a second semiconductor element layer on a second surface of the second semiconductor substrate,
wherein the second semiconductor structure comprises:
a first via structure extending vertically in the second semiconductor substrate and connected to the second semiconductor element layer;
and
a passivation layer covering a third surface of the second semiconductor substrate, wherein the third surface is opposite the second surface,
wherein the second semiconductor substrate defines a recess region on the third surface, wherein the recess region surrounds the first via structure, and
wherein the passivation layer includes a protrusion that fills the recess region, the passivation layer being in contact with the first via structure.

6 more elements

A semiconductor memory device comprising:

a first semiconductor substrate comprising a cell array region;
a first interlayer insulating layer covering the first semiconductor substrate;
first wirings in the first interlayer insulating layer and electrically connected to the cell array region;
a first bonding layer on the first interlayer insulating layer;
a second semiconductor substrate on the first bonding layer, the second semiconductor substrate comprising a logic region electrically connected to the cell array region;
a transistor on a top surface of the second semiconductor substrate on the logic region;
a second interlayer insulating layer covering the top surface of the second semiconductor substrate;
second wirings in the second interlayer insulating layer and electrically connected to the transistor;
a passivation layer covering a bottom surface of the second semiconductor substrate;
a second bonding layer covering a bottom surface of the passivation layer and in contact with the first bonding layer;
and
a via structure in a via hole that extends vertically in the second semiconductor substrate,
wherein the second semiconductor substrate comprises an inclined surface connecting an inner surface of the via hole with the bottom surface of the second semiconductor substrate,
wherein the via structure is horizontally spaced apart from the bottom surface of the second semiconductor substrate,
wherein the second bonding layer includes a via pattern, and
wherein the via pattern extends in the passivation layer to connect to a bottom surface of the via structure, and is horizontally spaced apart from the bottom surface of the second semiconductor substrate.

13 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20