All-tungsten scheme for source/drain contact, source/drain via, and gate via

A semiconductor device, comprising:

• a channel region on a substrate and an S/D feature adjacent to the channel region;
• a silicide feature over the S/D feature;
• a gate structure over the channel region;
• gate spacers along sidewalls of the gate structure;
• a first interlayer dielectric (ILD) layer over the gate structure;
• an etch stop layer over the first ILD layer;
• a second ILD layer over the etch stop layer;
• a tungsten S/D contact over the S/D feature and interfacing with the first ILD layer, wherein the tungsten S/D contact is spaced apart from the gate structure by one of the gate spacers, wherein the tungsten S/D contact is electrically coupled to the S/D feature by way of the silicide feature;
• and
• a tungsten S/D via landing on the S/D contact and interfacing with the second ILD layer.

A semiconductor device, comprising:

• a channel region on a substrate and an S/D feature adjacent to the channel region;
• a gate structure over the channel region, wherein the gate structure includes a gate electrode over a gate dielectric layer and gate spacers along sidewalls of the gate structure, and the gate dielectric layer has a higher dielectric constant than the gate spacers;
• a first interlayer dielectric (ILD) layer over the gate structure;
• a second ILD layer over the first ILD layer;
• a silicide feature over the S/D feature;
• a tungsten seed layer over the silicide feature;
• a tungsten S/D contact disposed on the tungsten seed layer and embedded within the first ILD layer, wherein the tungsten S/D contact is electrically coupled to the S/D feature by way of the silicide feature and the tungsten seed layer;
• and
• a tungsten S/D via disposed on the S/D contact and embedded within the second ILD layer, wherein the tungsten seed layer has a different material composition than the tungsten S/D contact and the tungsten S/D via.