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US 2026/0282847 A1Published application
Stacked die memory sparing device and method
AssigneeMicron Technology, Inc.
InventorsSai Krishna Mylavarapu, Todd A. Marquart
Life of this patent
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Abstract
Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example methods include determining wafer level maps by mapping a defect distribution across multiple wafers. Example methods further include aligning wafers based on the wafer level maps to improve yield within die stacks. Example semiconductor devices and methods further include a controller circuit to allocate at least one memory die sub-portion.
Claims19
A method of manufacturing a memory device, comprising:
- forming a plurality of first memory dies on a first wafer;
- forming plurality of second memory dies on a number of subsequent wafers;
- determining wafer level maps by mapping a defect distribution across the first wafer and the number of subsequent wafers;
- aligning the first wafer with one or more of the number of subsequent wafers based on the wafer level maps to improve yield within die stacks;
- coupling a number of wafers including at least the first wafer and selected wafers from the number of subsequent wafers to form a wafer stack;
- and
- separating individual die stacks from the wafer stack.
4 more elements
A semiconductor memory device, comprising;
- a stack of memory dies;
- at least one spare memory die within the stack of memory dies, the at least one spare memory die subdivided into a number of memory die sub-portions;
- and
- a memory controller circuit stacked with the stack of memory dies;
- wherein the memory controller circuit is configured to allocate at least one memory die sub-portion to make up for a defective portion of one memory die in the stack of memory dies.
2 more elements
An electronic device, comprising;
- one or more processors;
- a memory device coupled to the one or more processors, the memory device including:
- a stack of memory dies;
- at least one spare memory die within the stack of memory dies, the at least one spare memory die subdivided into a number of memory die sub-portions;
- and
- a memory controller circuit stacked with the stack of memory dies;
- wherein the memory controller circuit is configured to allocate at least one memory die sub-portion to make up for a defective portion of one memory die in the stack of memory dies.
4 more elements
Dependencies are inferred from the claim text.