Image sensor including conductive pattern

An image sensor, comprising:

• a substrate including pixel regions including each photodiode;
• a lower isolation pattern defining the pixel regions within the substrate;
• a floating diffusion region configured to store charges transferred from the photodiode, on one surface of the substrate;
• a source follower transistor including a gate pattern disposed adjacently to the lower isolation pattern and source/drain regions disposed on both sides of the gate pattern, and configured to transmit a signal by amplifying the charges of the floating diffusion region;
• and
• an upper isolation pattern disposed on the lower isolation pattern on the one surface of the substrate and adjacent to the gate pattern of the source follower transistor,
• wherein at least one of the source/drain regions of the source follower transistor includes a semiconductor conductive layer disposed on the adjacent upper isolation pattern, overlapping the lower isolation pattern in a vertical direction, and including a material different from a material of the substrate.

An image sensor, comprising:

• a pixel array including a plurality of pixel regions arranged in a direction, parallel to one surface of a substrate, each of the plurality of pixel regions having at least one photodiode inside the substrate, a color filter disposed on the other surface of the substrate opposite to the one surface and at least one element disposed on the one surface;
• and
• a logic circuit obtaining a pixel signal from the plurality of pixel regions,
• wherein the pixel array includes:
• a floating diffusion region disposed on each of the plurality of pixel regions, and configured to store charges transferred from the photodiode, on the one surface of the substrate;
• circuit elements transmitting a photoelectric signal according to the charges of the floating diffusion region;
• and
• an upper isolation pattern defining the floating diffusion region and the circuit elements on the one surface of the substrate,
• wherein at least one of the circuit elements includes:
• a gate pattern disposed on the one surface of the substrate;
• and
• source/drain regions disposed on both side surfaces of the gate pattern, and
• wherein at least one of the source/drain regions includes a conductive layer disposed on the upper isolation pattern, contacting the substrate below the gate pattern, and including a different material from the substrate.