Eco base cell structure
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Tsmc Nanjing Company, Limited
InventorsXin Jian CUI, Liu HAN
Life of this patent
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Abstract
An IC structure includes first through third n-wells aligned in a first direction in a semiconductor substrate, wherein the second n-well is between the first and third n-wells, a first tap structure overlying and electrically connected to the first n-well, second and third tap structures overlying and electrically connected to the second n-well, a fourth tap structure overlying and electrically connected to the third n-well, a first metal segment extending in the first direction, overlying each of the first through fourth tap structures, and electrically connected to each of the first and fourth tap structures, and a second metal segment extending in the first direction and overlying and electrically connected to each of the second and third tap structures
Claims20
An integrated circuit (IC) structure comprising:
- first through third n-wells aligned in a first direction in a semiconductor substrate, wherein the second n-well is between the first and third n-wells;
- a first tap structure overlying and electrically connected to the first n-well;
- second and third tap structures overlying and electrically connected to the second n-well;
- a fourth tap structure overlying and electrically connected to the third n-well;
- a first metal segment extending in the first direction, overlying each of the first through fourth tap structures, and electrically connected to each of the first and fourth tap structures;
- and
- a second metal segment extending in the first direction and overlying and electrically connected to each of the second and third tap structures.
An integrated circuit (IC) structure comprising:
- first through third n-wells aligned in a first direction in a semiconductor substrate, wherein the second n-well is between the first and third n-wells;
- a first tap structure comprising a first via overlying and electrically connected to the first n-well;
- second and third tap structures comprising respective second and third vias overlying and electrically connected to the second n-well;
- a fourth tap structure comprising a fourth via overlying and electrically connected to the third n-well;
- a first metal segment extending in the first direction, overlying each of the first through fourth tap structures, and electrically connected to each of the first and fourth vias;
- and
- a second metal segment extending in the first direction and overlying and electrically connected to each of the second and third vias.
An integrated circuit (IC) structure comprising:
- first through third n-wells aligned in a first direction in a semiconductor substrate, wherein the second n-well is between the first and third n-wells;
- a first tap structure overlying and electrically connected to the first n-well;
- second and third tap structures overlying and electrically connected to the second n-well;
- a function region comprising pluralities of active areas, conductive segments, and gate structures arranged in the second n-well between the second and third tap structures;
- a fourth tap structure overlying and electrically connected to the third n-well;
- a first metal segment extending in the first direction, overlying each of the first through fourth tap structures and the function region, and electrically connected to each of the first and fourth tap structures;
- and
- a second metal segment extending in the first direction, overlying each of the second and third tap structures and the function region, and electrically connected to each of the second and third tap structures.
Dependencies are inferred from the claim text.