Gate structures

A method, comprising:

• forming a channel region over a substrate, the channel region comprising a plurality of nanostructures;
• forming an isolation feature over the substrate and adjacent to a sidewall of the channel region;
• and
• forming a gate structure over the channel region and interfacing a top surface of the isolation feature, wherein the forming of the gate structure comprises:
• depositing a gate dielectric layer over the plurality of nanostructures and the isolation feature,
• depositing a p-type work function metal layer over the gate dielectric layer,
• soaking the p-type work function metal layer using a silicon-containing gas,
• after the soaking, depositing an n-type work function metal layer over the p-type work function metal layer and the isolation feature, wherein the n-type work function metal layer has a non-uniform thickness.

A semiconductor device, comprising:

• a first base fin and a second base fin over a substrate;
• an isolation feature over the substrate and interfacing sidewalls of the first base fin and the second base fin;
• a first plurality of nanostructures disposed over the first base fin;
• a second plurality of nanostructures disposed over the second base fin;
• a gate dielectric layer wrapping around the first plurality of nanostructures and the second plurality of nanostructures, the gate dielectric layer being disposed over top surfaces of the first base fin, the second base fin, and the isolation feature;
• a first work function layer wrapping around the second plurality of nanostructures and disposed over the second base fin;
• a silicon-containing layer over the first work function layer;
• a second work function layer comprising a first portion wrapping around the first plurality of nanostructures over the first base fin and a second portion disposed over the silicon-containing layer, the first portion and the second portion having different thicknesses.