Semiconductor device including gate electrode on two spaced apart semiconductor patterns

A semiconductor device, comprising:

• a substrate including an active pattern;
• a channel pattern on the active pattern, the channel pattern comprising a first semiconductor pattern and a second semiconductor pattern vertically spaced apart from each other;
• a source/drain pattern connected to the first and second semiconductor patterns;
• a gate electrode on the first and second semiconductor patterns;
• and
• a gate dielectric layer between the gate electrode and the first semiconductor pattern and between the gate electrode and the second semiconductor pattern,
• wherein an inner region is defined between a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern,
• wherein the gate dielectric layer comprises an inner spacer in the inner region,
• wherein the gate electrode comprises an inner electrode in the inner spacer,
• wherein the top surface of the first semiconductor pattern is convexly curved toward the inner electrode,
• wherein the bottom surface of the second semiconductor pattern is convexly curved toward the inner electrode, and
• wherein the inner spacer comprises:
• a first part between the inner electrode and the bottom surface of the second semiconductor pattern;
• a second part between the inner electrode and the source/drain pattern;
• and
• a third part connecting the first part and the second part to each other.

A semiconductor device, comprising:

• a substrate including an active pattern;
• a channel pattern on the active pattern, the channel pattern comprising a first semiconductor pattern and a second semiconductor pattern vertically spaced apart from each other;
• a source/drain pattern connected to the first and second semiconductor patterns;
• a gate electrode on the first and second semiconductor patterns;
• and
• a gate dielectric layer between the gate electrode and the first semiconductor pattern and between the gate electrode and the second semiconductor pattern,
• wherein an inner region is defined between a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern,
• wherein the gate dielectric layer comprises an inner spacer in the inner region,
• wherein the gate electrode comprises an inner electrode in the inner spacer,
• wherein the inner spacer comprises:
• a first part between the inner electrode and the second semiconductor pattern;
• a second part between the inner electrode and the source/drain pattern;
• and
• an edge protrusion connecting the first part and the second part to each other, and
• wherein the edge protrusion protrudes into the second semiconductor pattern.