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US 2026/0282480 A1Published application
Method of reducing metal gate resistance for next generation nmos device application
AssigneeApplied Materials, Inc.
InventorsSrinivas Gandikota, Yixiong Yang, Yongjing Lin, Tuerxun Ailihumaer, Tengzhou Ma, Yuanhua Zheng, Zhihui Liu, Shih Chung Chen, Janardhan Devrajan, Yi Xu, Yu Lei, Mandyam Sriram
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Abstract
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.
Claims20
A method of reducing gate resistance in an NMOS device, the method comprising:
- depositing a liner layer on a metal gate stack;
- removing a portion of the liner layer;
- and
- depositing a low resistivity metal fill on the liner layer.
1 more element
Dependencies are inferred from the claim text.