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US 2026/0282459 A1Published application
Semiconductor transistor mesa isolation structure and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzu-Wen Shih, Der-Ming Kuo, Ching-Heng Liu, Shih-Hsiang Tai
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Abstract
A semiconductor transistor mesa isolation structure and method of forming the same including a mesa isolation structure located between a first gate and a second gate, the mesa isolation structure including sidewalls latitudinally offset from each of the first gate and the second gate, and the mesa isolation structure extending through an interior of a barrier layer of the semiconductor transistor, and the mesa isolation structure formed with a dielectric material.
Claims20
A method of forming a semiconductor transistor structure comprising:
- forming a carrier channel layer structure on a semiconductor substrate, the carrier channel layer structure including a first side oriented towards the substrate and a second side oriented opposite the first side;
- forming a barrier layer structure on the carrier channel layer structure, the barrier layer structure including a first side oriented towards the carrier channel layer structure and a second side oriented opposite the first side the barrier layer structure, and the carrier channel layer structure and the barrier layer structure providing a heterojunction interface including a 2 dimensional electron gas (2DEG) conductive channel;
- forming a first gate layer on the second side of barrier layer structure and a second gate layer on the second side of barrier layer structure, the first gate layer and the second gate layer latitudinally offset from each other along a direction of the conductive channel;
- forming a mesa isolation structure located between the first gate layer and the second gate layer, the mesa isolation structure including sidewalls latitudinally offset from each of the first gate layer and the second gate layer, the mesa isolation structure extending from the second side of the barrier layer through at least an interior of the barrier layer structure, and the mesa isolation structure formed with a dielectric material;
- and
- forming a dielectric region on the mesa isolation structure, the dielectric region extending from the first gate layer to the second gate layer.
3 more elements
A semiconductor device comprising:
- a carrier channel layer structure on a semiconductor substrate, the carrier channel layer structure including a first side oriented towards the substrate and a second side oriented opposite the first side;
- a barrier layer structure on the carrier channel layer structure, the barrier layer structure including a first side oriented towards the carrier channel layer structure and a second side oriented opposite the first side the barrier layer structure, and the carrier channel layer structure and the barrier layer structure providing a heterojunction interface including a 2 dimensional electron gas (2DEG) conductive channel;
- a first gate layer on the second side of barrier layer structure and a second gate layer on the second side of barrier layer structure, the first gate layer and the second gate layer latitudinally offset from each other along a direction of the conductive channel;
- a mesa isolation structure between the first gate layer and the second gate layer, the mesa isolation structure including sidewalls latitudinally offset from each of the first gate layer and the second gate layer, the mesa isolation structure extending from the second side of the barrier layer through an interior of the barrier layer structure, and the mesa isolation structure formed with a dielectric material;
- and
- a dielectric region on the mesa isolation structure, the dielectric region extending from the first gate layer to the second gate layer.
3 more elements
A method of forming an integrated circuit (IC) including a mesa isolation structure a high electron mobility transistor (HEMT) structure comprising:
- epitaxially growing a carrier channel layer structure on a semiconductor substrate, the carrier channel layer structure including a first side oriented towards the substrate and a second side oriented opposite the first side;
- epitaxially growing a barrier layer structure on the carrier channel layer structure, the barrier layer structure including a first side oriented towards the carrier channel layer structure and a second side oriented opposite the first side the barrier layer structure, and the carrier channel layer structure and the barrier layer structure providing a heterojunction interface including a 2 dimensional electron gas (2DEG) conductive channel;
- using a photolithographic process to form a first gate layer on the second side of barrier layer structure and a second gate layer on the second side of barrier layer structure, the first gate layer and the second gate layer latitudinally offset from each other along a direction of the conductive channel;
- etching a mesa trench to form sidewalls of a mesa isolation structure, the mesa trench located between the first gate layer and the second gate layer, the mesa trench including sidewalls latitudinally offset from each of the first gate layer and the second gate layer, and the mesa trench extending from the second side of the barrier layer through an interior of the barrier layer structure;
- forming a mesa isolation structure within the sidewalls of the mesa trench, the mesa isolation structure including a dielectric material deposited within the mesa trench;
- forming a dielectric region on the mesa isolation structure, the dielectric region extending from the first gate layer to the second gate layer;
- and
- patterning a gate metal line which electrically connects the first gate layer and the second gate layer, the gate metal line formed on the dielectric region.
5 more elements
Dependencies are inferred from the claim text.