Reducing band-to-band tunneling in semiconductor devices

An integrated circuit structure, comprising:

• a nanowire comprising germanium;
• a gate structure surrounding the nanowire, the gate structure including a gate dielectric and a gate electrode, the gate dielectric between the nanowire and the gate electrode;
• a source region and a drain region, the nanowire between the source region and the drain region, wherein one of the source region or the drain region comprises a semiconductor material having a germanium concentration in excess of 75 atomic percent;
• and
• a spacer between the nanowire and the one of the source region or the drain region, the spacer extending under one or both of the gate electrode and the gate dielectric, the spacer including a semiconductor material comprising silicon, germanium, and carbon.

A computing device comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure comprising:
• a nanowire comprising germanium;
• a gate structure surrounding the nanowire, the gate structure including a gate dielectric and a gate electrode, the gate dielectric between the nanowire and the gate electrode;
• a source region and a drain region, the nanowire between the source region and the drain region, wherein one of the source region or the drain region comprises a semiconductor material having a germanium concentration in excess of 75 atomic percent;
• and
• a spacer between the nanowire and the one of the source region or the drain region, the spacer extending under one or both of the gate electrode and the gate dielectric, the spacer including a semiconductor material comprising silicon, germanium, and carbon.